1. Field of the Invention
The present invention relates to a semiconductor device. In particular, the present invention relates to a semiconductor device provided with an electrostatic discharge (ESD) protection circuit that protects destruction of an internal circuit due to an ESD stress or an application of a surge.
2. Description of the Related Art
An ESD protection circuit is incorporated in a semiconductor integrated circuit so as to protect an internal circuit against a surge applied to an input and output pad. One of well-known topologies of the ESD protection circuit is a circuit topology using a silicon controlled rectifier (SCR). Japanese Laid Open Patent Application (JP-P2003-203985A) discloses an ESD protection circuit using an SCR. FIG. 1 is a cross-sectional view showing a structure of the ESD protection circuit disclosed in the patent document.
As shown in FIG. 1, the ESD protection circuit within the public domain has an SCR region 2 and a trigger circuit region 3 which are integrated on a P-type semiconductor substrate 1. The trigger circuit region 3 is isolated from the SCR region 2 by an STI (shallow trench isolation) layer 4 as an insulator.
An N-well 5 is formed in the SCR region 2, and an N+ diffusion layer 6 and a P+ diffusion layer 7 are formed in a surface portion of the N-well 5. Further, an N+ diffusion layer 8 and a P+ diffusion layer 9 are formed in a portion of the SCR region 2 outside of the N-well 5. The N+ diffusion layer 6, the P+ diffusion layer 7, the N+ diffusion layer 8 and the P+ diffusion layer 9 are isolated from one another by STI layers 10 as insulators. The P+ diffusion layer 7, the N-well 5, a portion near a surface of the P-type semiconductor substrate 1, and the N+ diffusion layer 8 function as an SCR having a pnpn structure. More specifically, the P+ diffusion layer 7 functions as an anode of the SCR, the N-well 5 functions as a base thereof, and the N+ diffusion layer 8 functions as a cathode thereof. On the other hand, the N+ diffusion layer 6 and the P+ diffusion layer 9 function as contact layers for realizing electrical connections to the N-well 5 and the P-type semiconductor substrate 1, respectively. The P+ diffusion layer 7 is connected to an input and output (I/O) pad 11 used for inputting and outputting a signal to and from an internal circuit (not shown). The N+ diffusion layer 8 and the P+ diffusion layer 9 are connected in common to a grounding terminal 12.
The trigger circuit region 3 is a region in which a trigger circuit that turns on the above-mentioned SCR when a surge is applied to the I/O pad 11 is formed. In the ESD protection circuit shown in FIG. 1, an NMOS transistor 13 having a source and a gate connected in common to the grounding terminal 12 is used as the trigger circuit. More specifically, a source region 14 and a drain region 15 of N+ conductive type are formed in a surface portion of the P-type semiconductor substrate 1. Further, a gate insulating layer 16 is formed on the surface of the P-type semiconductor substrate 1, and a gate electrode 17 is formed on the gate insulating layer 16. The gate electrode 17 typically includes a polysilicon layer 17a and a silicide layer 17b formed on the polysilicon layer 17a. Examples of the silicide layer 17b include a titanium silicide layer, a cobalt silicide layer, and a tungsten silicide layer. The drain region 15 is electrically connected to the N+ diffusion layer 6 in the SCR region 2 through a metal wiring 18. The source region 14 and the gate electrode 17 are connected to the grounding terminal 12.
FIG. 2 shows an equivalent circuit of the ESD protection circuit shown in FIG. 1. The ESD protection circuit shown in FIG. 1 equivalently functions as a circuit that includes a PNP transistor 21, an NPN transistor 22, a substrate resistance RSUB, an N-well resistance RNW and the NMOS transistor 13. An emitter of the PNP transistor 21 is connected to the I/O pad 11, a collector thereof is connected to the grounding terminal 12 through the substrate resistance RSUB, and a base thereof is connected to a collector of the NPN transistor 22. A base of the NPN transistor 22 is connected to the collector of the PNP transistor 21, and an emitter thereof is connected to the grounding terminal 12. With regard to the NMOS transistor 13 that functions as the trigger circuit, a drain thereof is connected to the base of the PNP transistor 21 through the N-well resistance RNW and the metal wiring 18, and a source and a gate thereof are connected to the grounding terminal 12.
When a surge voltage is applied to the I/O pad 11, the ESD protection circuit shown in FIG. 1 operates as follows to protect the internal circuit. When the surge voltage is applied to the I/O pad 11, the surge voltage is applied to the drain of the NMOS transistor 13 through the emitter and base of the PNP transistor 21. If the surge voltage causes breakdown of the NMOS transistor 13, then a trigger current flows from the base of the PNP transistor 21 toward the grounding terminal 12, and the PNP transistor 21 is thereby turned on. When the PNP transistor 21 is turned on, an emitter-collector current flows from the emitter to the collector of the PNP transistor 21. The emitter-collector current flows into the grounding terminal 12 through the substrate resistance RSUB. When the emitter-collector current flows through the substrate resistance RSUB, a base potential of the NPN transistor 22 is increased due to a voltage drop at the substrate resistance RSUB. When the base potential of the NPN transistor 22 is increased, a base current flows in the NPN transistor 22, and the NPN transistor 22 is thereby turned on. When the NPN transistor 22 is turned on, the surge voltage applied to the I/O pad 11 is discharged through the NPN transistor 22, and thus the internal circuit is protected.
The ESD protection circuit shown in FIG. 1 is advantageous in that a high discharge capability and a low trigger voltage can be simultaneously ensured because the SCR and the trigger circuit are isolated from each other. Specifically, the ESD protection circuit shown in FIG. 1 has the following advantages. First, since the SCR is isolated from the trigger circuit, a length of the base of the SCR can be designed to be small. This can enhance the discharge capability of the ESD protection circuit. Secondly, since the trigger circuit can be designed irrespective of the SCR, the trigger voltage can be arbitrarily designed in the ESD protection circuit shown in FIG. 1. This means that the ESD protection circuit shown in FIG. 1 satisfies both the high discharge capability and the low trigger voltage.